MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 410

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Queued Analog-to-Digital Converter (QADC)
Technical Data
410
1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor
2. Access results in the module generating an access termination transfer error if not in test mode.
3. Read/writes have no effect and the access terminates with a transfer error exception.
0x00ca_0014–
0x00ca_0200–
0x00ca_0280–
0x00ca_0300–
0x00ca_0380–
0x00ca_0000
0x00ca_0002
0x00ca_0004
0x00ca_0006
0x00ca_0008
0x00ca_000a
0x00ca_000c
0x00ca_000e
0x00ca_0010
0x00ca_0012
0x00ca_027e
0x00ca_037e
only addresses have no effect and result in a cycle termination transfer error.
0x00ca_01fe
0x00ca_02fe
0x00ca_03fe
Address
MSB
Port QA data register (PORTQA)
Freescale Semiconductor, Inc.
For More Information On This Product,
QADC module configuration register (QADCMCR)
Queued Analog-to-Digital Converter (QADC)
Right justified, unsigned result register (RJURR)
Left justified, unsigned result register (LJURR)
Table 18-2. QADC Memory Map
Left justified, signed result register (LJSRR)
Port QA data direction register (DDRQA)
Conversion command word table (CCW)
QADC test register (QADCTEST)
QADC control register 0 (QACR0)
QADC control register 1 (QACR1)
QADC control register 2 (QACR2)
QADC status register 0 (QASR0)
QADC status register 1 (QASR1)
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Reserved
Reserved
Port QB data register (PORTQB)
(3)
(3)
(2)
LSB
MMC2107 – Rev. 2.0
Access
MOTOROLA
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
—
—
S
S
(1)