MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 419

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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18.8.5.2 Control Register 1
MMC2107 – Rev. 2.0
MOTOROLA
Address: 0x00ca_000c and 0x00ca_000d
Reset:
Reset:
Read:
Read:
Write:
Write:
Control register 1 (QACR1) is the mode control register for the operation
of queue 1. The applications software defines the queue operating mode
for the queue and may enable a completion and/or pause interrupt. Most
of the bits are typically written once when the software initializes the
QADC and not changed afterward.
Stop mode resets the register ($0000)
Read: Anytime
Write: Anytime except stop mode
CIE1 — Queue 1 Completion Interrupt Enable Bit
CIE1 enables an interrupt upon completion of queue 1. The interrupt
request is initiated when the conversion is complete for the CCW in
queue 1.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = Enable interrupt after the conversion of the sample requested
0 = Disable queue 1 completion interrupt
Bit 15
CIE1
Bit 7
0
0
0
Figure 18-9. QADC Control Register 1 (QACR1)
by the last CCW in queue 1
Go to: www.freescale.com
= Writes have no effect and the access terminates without a transfer error exception.
PIE1
14
0
6
0
0
SSE1
13
0
0
5
0
0
MQ112
12
0
4
0
0
Queued Analog-to-Digital Converter (QADC)
MQ111
11
0
3
0
0
MQ110
10
0
2
0
0
Register Descriptions
MQ19
9
0
1
0
0
Technical Data
MQ18
Bit 8
Bit 0
0
0
0
419

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