MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 431

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

MMC2107 – Rev. 2.0
MOTOROLA
TOR1 — Queue 1 Trigger Overrun
PF2 is maintained by the QADC regardless of whether the
corresponding interrupts are enabled. The software may poll PF2 to
find out when the QADC has reached a pause in scanning a queue.
The software acknowledges that it has detected a pause flag being
set by writing a 0 to PF2 after the bit was last read as a 1.
See
TOR1 indicates that an unexpected trigger event has occurred for
queue 1. TOR1 can be set only while queue 1 is in the active state.
A trigger event generated by a transition on the external trigger pin or
by the periodic/interval timer may be captured as a trigger overrun.
TOR1 cannot occur when the software-initiated single-scan mode or
the software-initiated continuous-scan mode are selected.
TOR1 occurs when a trigger event is received while a queue is
executing and before the scan has completed or paused. TOR1 has
no effect on the queue execution.
After a trigger event has occurred for queue 1, and before the scan
has completed or paused, additional queue 1 trigger events are not
retained. Such trigger events are considered unexpected, and the
QADC sets the TOR1 error status bit. An unexpected trigger event
may be a system overrun situation, indicating a system loading
mismatch.
In external gated continuous-scan mode, the definition of TOR1 has
been redefined. In the case when queue 1 reaches an end-of-queue
condition for the second time during an open gate, TOR1 becomes
set. This is considered an overrun condition. In this case CF1 has
been set for the first end-of-queue 1 condition and then TOR1
becomes set for the second end-of-queue 1 condition. For TOR1
to be set, software must not clear CF1 before the second
end-of-queue 1.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = queue 2 has reached a pause.
0 = queue 2 has not reached a pause.
Table 18-7
Go to: www.freescale.com
for a summary of pause response in all scan modes.
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
Technical Data
431