MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 434

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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Queued Analog-to-Digital Converter (QADC)
Technical Data
434
Only one queue can be active at a time. Either or both queues can be
in the paused state. A queue is paused when the previous CCW
executed from that queue had the pause bit set. The QADC does not
execute any CCWs from the paused queue until a trigger event
occurs. Consequently, the QADC can service queue 2 while queue 1
is paused.
Only queue 2 can be in the suspended state. When a trigger event
occurs on queue 1 while queue 2 is executing, the current queue 2
conversion is aborted. The queue 2 status is reported as suspended.
Queue 2 transitions back to the active state when queue 1 becomes
idle or paused.
A trigger pending state is required since both queues cannot be active
at the same time. The status of queue 2 is changed to trigger pending
when a trigger event occurs for queue 2 while queue 1 is active. In the
opposite case, when a trigger event occurs for queue 1 while queue 2
is active, queue 2 is aborted and the status is reported as queue 1
active, queue 2 suspended. So due to the priority scheme, only
queue 2 can be in the trigger pending state.
Two transition cases cause the queue 2 status to be trigger pending
before queue 2 is shown to be in the active state. When queue 1 is
active and there is a trigger pending on queue 2, after queue 1
completes or pauses, queue 2 continues to be in the trigger pending
state for a few clock cycles. The fleeting status conditions are:
Figure 18-12
as the QADC goes through the transition from queue 1 active to
queue 2 active.
The queue status field is affected by the stop mode. Since all of the
analog logic and control registers are reset, the queue status field is
reset to queue 1 idle, queue 2 idle.
During the debug mode, the queue status field is not modified. The
queue status field retains the status it held prior to freezing. As a
result, the queue status can show queue 1 active, queue 2 idle, even
though neither queue is being executed during freeze.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
• queue 1 idle with queue 2 trigger pending
• queue 1 paused with queue 2 trigger pending
Go to: www.freescale.com
displays the status conditions of the queue status field
MMC2107 – Rev. 2.0
MOTOROLA

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