MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 438

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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Queued Analog-to-Digital Converter (QADC)
Technical Data
438
NOTE:
NOTE:
Read: Anytime except reads during stop mode are invalid
Write: Anytime except stop mode
P — Pause Bit
The P bit does not cause the queue to pause in the software controlled
modes or external gated modes.
BYP — Sample Amplifier Bypass Bit
BYP is maintained for software compatibility but has no functional
benefit to this version of the module.
IST[0:1] — Input Sample Time Field
The pause bit allows software to create subqueues within queue 1
and queue 2. The QADC performs the conversion specified by the
CCW with the pause bit set, and then the queue enters the pause
state. Another trigger event causes execution to continue from the
pause to the next CCW.
Setting the BYP field in the CCW enables the amplifier bypass mode
for a conversion and subsequently changes the timing. The initial
sample time is eliminated, reducing the potential conversion time by
two QCLKs. However, due to internal RC effects, a minimum final
sample time of four QCLKs must be allowed. When using this mode,
the external circuit should be of low source impedance. Loading
effects of the external circuitry need to be considered, since the
benefits of the sample amplifier are not present.
The IST field allows software to specify the length of the sample
window. Provision is made to vary the input sample time, through
software control, to offer flexibility in the source impedance of the
circuitry providing the QADC analog channel inputs. Longer sample
times permit more accurate A/D conversions of signals with higher
source impedances.
Table 18-9
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = Enter pause state after execution of current CCW
0 = Do not enter pause state after execution of current CCW
1 = Amplifier bypass mode enabled
0 = Amplifier bypass mode disabled
Go to: www.freescale.com
shows the four selectable input sample times.
MMC2107 – Rev. 2.0
MOTOROLA

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