MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 449

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

18.9.3.5 Digital-to-Analog Converter (DAC) Array
18.9.3.6 Comparator
18.9.3.7 Bias
18.9.3.8 Successive-Approximation Register
MMC2107 – Rev. 2.0
MOTOROLA
The digital-to-analog converter (DAC) array consists of binary-weighted
capacitors and a resistor-divider chain. The reference voltages, VRH
and VRL, are used by the DAC to perform ratiometric conversions. The
DAC also converts the following three internal channels:
The DAC array serves to provide a mechanism for the successive
approximation A/D conversion.
Resolution begins with the most significant bit (MSB) and works down to
the least significant bit (LSB). The switching sequence is controlled by
the comparator and SAR logic. The sample capacitor samples and holds
the voltage to be converted.
During the approximation process, the comparator senses whether the
digitally selected arrangement of the DAC array produces a voltage level
higher or lower than the sampled input. The comparator output feeds
into the SAR which accumulates the A/D conversion result sequentially,
beginning with the MSB.
The bias circuit is controlled by the STOP signal to power-up and
power-down all the analog circuits.
The input of the SAR is connected to the comparator output. The SAR
sequentially receives the conversion value one bit at a time, starting with
the MSB. After accumulating the 10 bits of the conversion result, the
SAR data is transferred to the appropriate result location, where it may
be read from the IPbus by user software.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
V
V
(V
RH
RL
RH
— reference voltage low
— reference voltage high
–V
Go to: www.freescale.com
RL
)/2 — reference voltage
Queued Analog-to-Digital Converter (QADC)
Functional Description
Technical Data
449