MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 451

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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18.10.1.1 Queue Priority
MMC2107 – Rev. 2.0
MOTOROLA
Queue 1 has priority over queue 2 execution. These cases show the
conditions under which queue 1 asserts its priority:
The pause feature can be used to divide queue 1 and/or queue 2 into
multiple subqueues. A subqueue is defined by setting the pause bit in
the last CCW of the subqueue.
Figure 18-22
create subqueues. Queue 1 is shown with four CCWs in each subqueue
and queue 2 has two CCWs in each subqueue.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
When a queue is not active, a trigger event for queue 1 or queue
2 causes the corresponding queue execution to begin.
When queue 1 is active and a trigger event occurs for queue 2,
queue 2 cannot begin execution until queue 1 reaches completion
or the paused state. The status register records the trigger event
by reporting the queue 2 status as trigger pending. Additional
trigger events for queue 2, which occur before execution can
begin, are captured as trigger overruns.
When queue 2 is active and a trigger event occurs for queue 1, the
current queue 2 conversion is aborted. The status register reports
the queue 2 status as suspended. Any trigger events occurring for
queue 2 while queue 2 is suspended are captured as trigger
overruns. Once queue 1 reaches the completion or the paused
state, queue 2 begins executing again. The programming of the
RESUME bit in QACR2 determines which CCW is executed in
queue 2.
When simultaneous trigger events occur for queue 1 and queue 2,
queue 1 begins execution and the queue 2 status is changed to
trigger pending.
Subqueues that are paused
Go to: www.freescale.com
shows the CCW format and an example of using pause to
Queued Analog-to-Digital Converter (QADC)
Technical Data
Digital Control
451

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