MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 455

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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MMC2107 – Rev. 2.0
MOTOROLA
QS
Q1
Q2
IDLE
0000
QS = 0011 and QS = 0111, are not shown because they exist only very
briefly between stable status conditions.
The first three examples in
and S3) show what happens when a new trigger event is recognized
before the queue has completed servicing the previous trigger event on
the same queue.
In situation S1
each queue while that queue is still working on the previously recognized
trigger event. The trigger overrun error status bit is set, and otherwise,
the premature trigger event is ignored. A trigger event which occurs
before the servicing of the previous trigger event is through does not
disturb the queue execution in progress.
Freescale Semiconductor, Inc.
Figure 18-23. CCW Priority Situation 1
Q1:
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
T1
IDLE
C1
TOR1
T1
Go to: www.freescale.com
C2
ACTIVE
1000
(Figure
C3
C4
18-23), one trigger event is being recognized on
CF1
Figure 18-23
0000
Q2:
T2
Queued Analog-to-Digital Converter (QADC)
C1
C2
ACTIVE
through
TOR2
0010
T2
C3
IDLE
C4
Figure 18-25
CF2
IDLE
0000
Technical Data
Digital Control
(S1, S2,
455

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