MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 465

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

18.10.2 Boundary Conditions
MMC2107 – Rev. 2.0
MOTOROLA
NOTE:
The queue operation boundary conditions are:
Multiple end-of-queue conditions may be recognized simultaneously,
although there is no change in the QADC behavior. For example, if BQ2
is set to CCW0, CCW0 contains the EOQ code, and a trigger event
occurs on queue 1, the QADC reads CCW0 and detects both
end-of-queue conditions. The completion flag is set and queue 1
becomes idle.
Boundary conditions also exist for combinations of pause and
end-of-queue. One case is when a pause bit is in one CCW and an
end-of-queue condition is in the next CCW. The conversion specified by
the CCW with the pause bit set completes normally. The pause flag is
set. However, since the end-of-queue condition is recognized, the
completion flag is also set and the queue status becomes idle, not
paused. Examples of this situation include:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
The first CCW in a queue contains channel 63, the end-of-queue
(EOQ) code. The queue becomes active and the first CCW is
read. The end-of-queue is recognized, the completion flag is set,
and the queue becomes idle. A conversion is not performed.
BQ2 (beginning of queue 2) is set at the end of the CCW table (63)
and a trigger event occurs on queue 2. The end-of-queue
condition is recognized, a conversion is performed, the completion
flag is set, and the queue becomes idle.
BQ2 is set to CCW0 and a trigger event occurs on queue 1. After
reading CCW0, the end-of-queue condition is recognized, the
completion flag is set, and the queue becomes idle. A conversion
is not performed.
BQ2 (beginning of queue 2) is set beyond the end of the CCW
table (64–127) and a trigger event occurs on queue 2. The
end-of-queue condition is recognized immediately, the completion
flag is set, and the queue becomes idle. A conversion is not
performed.
The pause bit is set in CCW5 and the channel 63 (EOQ) code is
in CCW6.
The pause is in CCW63.
During queue 1 operation, the pause bit is set in CCW20 and BQ2
points to CCW21.
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Queued Analog-to-Digital Converter (QADC)
Technical Data
Digital Control
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