MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 467

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

18.10.4 Disabled Mode
18.10.5 Reserved Mode
18.10.6 Single-Scan Modes
MMC2107 – Rev. 2.0
MOTOROLA
NOTE:
When the disabled mode is selected, the queue is not active. Trigger
events cannot initiate queue execution. When both queue 1 and queue 2
are disabled, wait states are not encountered for IPbus accesses of the
RAM. When both queues are disabled, it is safe to change the QCLK
prescaler values.
Reserved mode allows for future mode definitions. When the reserved
mode is selected, the queue is not active. It functions the same as
disabled mode.
When the application software wants to execute a single pass through a
sequence of conversions defined by a queue, a single-scan queue
operating mode is selected. By programming the MQ field in QACR1 or
QACR2, these modes can be selected:
Queue 2 cannot be programmed for external gated single-scan mode.
In all single-scan queue operating modes, the software must also enable
the queue to begin execution by writing the single-scan enable bit to a 1
in the queue’s control register. The single-scan enable bits, SSE1 and
SSE2, are provided for queue 1 and queue 2 respectively.
Until the single-scan enable bit is set, any trigger events for that queue
are ignored. The single-scan enable bit may be set to a 1 during the write
cycle, which selects the single-scan queue operating mode. The
single-scan enable bit is set through software, but will always read as
a 0. Once set, writing the single-scan enable bit to 0 has no effect. Only
the QADC can clear the single-scan enable bit. The completion flag,
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Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Software-initiated single-scan mode
External trigger single-scan mode
External gated single-scan mode
Interval timer single-scan mode
Go to: www.freescale.com
Queued Analog-to-Digital Converter (QADC)
Technical Data
Digital Control
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