MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 475

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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18.10.7.4 Periodic Timer Continuous-Scan Mode
MMC2107 – Rev. 2.0
MOTOROLA
an end-of-queue. However it is useful to take advantage of a smaller
queue in the manner described in the next paragraph.
In the event that the queue completes before the gate closes, a
completion flag will be set and the queue will roll over to the beginning
and continue conversions until the gate closes. If the gate remains open
and the completion flag is not cleared, when the queue completes a
second time the trigger overrun flag will be set and the queue will
roll-over again. The queue will continue to execute until the gate closes
or the mode is disabled.
If the gate closes before queue 1 completes execution, the current CCW
completes execution of queue 1 stops and QADC sets the PF1 bit to
indicate an incomplete queue. Software can read the CWPQ1 to
determine the last valid conversion in the queue. In this mode, if the gate
opens again, execution of queue 1 begins again. The start of queue 1 is
always the first CCW in the CCW table. Since the condition of the gate
is only sampled after each conversion during queue execution, closing
the gate for a period less than a conversion time interval does not
guarantee the closure will be captured.
The QADC includes a dedicated periodic timer for initiating a scan
sequence on queue 1 and/or queue 2. Software selects a programmable
timer interval ranging from 128 to 128K times the QCLK period in binary
multiples. The QCLK period is prescaled down from the IPbus MCU
clock.
When a periodic timer continuous-scan mode is selected for queue 1
and/or queue 2, the timer begins counting. After the programmed
interval elapses, the timer generated trigger event starts the appropriate
queue. Meanwhile, the QADC automatically performs the conversions in
the queue until an end-of-queue condition or a pause is encountered.
When a pause occurs, the QADC waits for the periodic interval to expire
again, then continues with the queue. Once end-of-queue has been
detected, the next trigger event causes queue execution to begin again
with the first CCW in the queue.
The periodic timer generates a trigger event whenever the time interval
elapses. The trigger event may cause the queue execution to continue
following a pause or queue completion, or may be considered a trigger
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
Queued Analog-to-Digital Converter (QADC)
Technical Data
Digital Control
475

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