MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 476

no-image

MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MMC2107CFCPV33
Manufacturer:
AMD
Quantity:
1 001
Part Number:
MMC2107CFCPV33
Manufacturer:
MOTOLOLA
Quantity:
745
Part Number:
MMC2107CFCPV33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MMC2107CFCPV33
Manufacturer:
MOT
Quantity:
2
Part Number:
MMC2107CFCPV33
Manufacturer:
FREESCALE
Quantity:
20 000
Queued Analog-to-Digital Converter (QADC)
18.10.8 QADC Clock (QCLK) Generation
Technical Data
476
CAUTION:
NOTE:
overrun. As with all continuous-scan queue operating modes, software
action is not needed between trigger events. Since both queues may be
triggered by the periodic/interval timer, see
Timer
Software enables the completion interrupt when using the periodic timer
continuous-scan mode. When the interrupt occurs, the software knows
that the periodically collected analog results have just been taken. The
software can use the periodic interrupt to obtain nonanalog inputs as
well, such as contact closures, as part of a periodic look at all inputs.
Figure 18-42
provides the timing for the A/D converter state machine which controls
the timing of the conversion. The QCLK is also the input to a 17-stage
binary divider which implements the periodic/interval timer. To retain the
specified analog conversion accuracy, the QCLK frequency (f
must be within the tolerance specified in
Specifications.
Before using the QADC, the software must initialize the prescaler with
values that put the QCLK within the specified range. Though most
software applications initialize the prescaler once and do not change it,
write operations to the prescaler fields are permitted.
For software compatibility with earlier versions of QADC, the definition of
PSL, PSH, and PSA have been maintained. However, the requirements
on minimum time and minimum low time no longer exist.
A change in the prescaler value while a conversion is in progress is likely
to corrupt the result from any conversion in progress. Therefore, any
prescaler write operation should be done only when both queues are in
the disabled modes.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
for a summary of periodic/interval timer reset conditions.
Go to: www.freescale.com
is a block diagram of the clock subsystem. The QCLK
Section 22. Electrical
18.10.9 Periodic/Interval
MMC2107 – Rev. 2.0
MOTOROLA
QCLK
)

Related parts for MMC2107CFCPV33