MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 477

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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MMC2107 – Rev. 2.0
MOTOROLA
QUEUE1 AND QUEUE2 TIMER
LOW-TIME
CYCLES (PSL) [3]
MODE RATE SELECTION [8]
CYCLES (PSH) [5]
INPUT SAMPLE TIME
SYSTEM CLOCK (f
FROM CCW [2]
HIGH-TIME
Figure 18-42. QADC Clock Subsystem Functions
sys
)
To accommodate wide variations of the main MCU clock frequency
(IPbus system clock – f
prescaler which divides the MCU system clock. To allow the A/D
conversion time to be maximized across the spectrum of system clock
frequencies, the QADC prescaler permits the frequency of QCLK to be
software selectable. It also allows the duty cycle of the QCLK waveform
to be programmable.
The software establishes the basic high phase of the QCLK waveform
with the PSH (prescaler clock high time) field in QACR0 and selects the
basic low phase of QCLK with the PSL (prescaler clock low time) field.
The combination of the PSH and PSL parameters establishes the
frequency of the QCLK.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
27 28 29 210 211 212 213 214 215 216 217
DOWN COUNTER
DETECT
ONE’S COMPLEMENT
PERIODIC TIMER/INTERVAL TIMER
ZERO
5-BIT
Go to: www.freescale.com
COMPARE
[5]
BINARY COUNTER
ATD CONVERTER
STATE MACHINE
[3]
SELECT
sys
LOAD PSH
), QCLK is generated by a programmable
SET QCLK
Queued Analog-to-Digital Converter (QADC)
GENERATE
CLOCK
PERIODIC/INTERVAL TRIGGER
EVENT FOR Q1 AND Q2 [2]
SAR CONTROL
SAR [10]
QCLK
f
sys
/2 to f
sys
Technical Data
/40
Digital Control
477

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