MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 48

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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General Description
1.4 Block Diagram
Technical Data
48
The basic structure of the MMC2107 is shown in
Freescale Semiconductor, Inc.
For More Information On This Product,
General-purpose input/output (GPIO):
– Up to 72 bits of GPIO
– Coherent 32-bit control
– Bit manipulation supported via set/clear functions
– Unused peripheral pins may be used as extra GPIO.
– Reduced drive control
M•CORE to IPbus interface:
– Complete interfacing between the M•CORE bus and the IPbus
– Minimum of three clocks for peripheral bus access
– Data alignment and data width conversion between the
External interface:
– Provides for direct support of asynchronous random-access
– Support interfacing to 16-bit and 32-bit data buses
– 32-bit external bidirectional data bus
– 23-bit address bus
– Four chip selects
– Byte/write enables
– Ability to boot from internal or external memories
– Internal bus activity is visible via show-cycle mode
– Special chip selects support replacement of GPIO with
– Emulation of internal page mode FLASH support
Joint Test Action Group (JTAG) support for system-level board
testing
peripheral bus
M•CORE 32-bit data bus and the IPbus peripheral data buses
memory (RAM), read-only memory (ROM), and FLASH
external logic (port replacement logic)
Go to: www.freescale.com
General Description
Figure
MMC2107 – Rev. 2.0
1-1.
MOTOROLA

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