MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 516

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

External Bus Interface Module (EBI)
19.8 Bus Exception Operation
19.8.1 Transfer Error Termination
19.8.2 Transfer Abort Termination
19.9 Emulation Support
19.9.1 Emulation Chip-Selects (CSE[1:0])
Technical Data
516
Normal bus cycle termination requires the assertion of the TA pin or the
internal transfer acknowledge signal. Minimal bus exception support is
provided by transfer error cycle termination. For transfer error cycle
termination, the external TEA pin or the internal transfer error
acknowledge signal is asserted. Transfer error cycle termination takes
precedence over normal cycle termination, provided TEA assertion
meets its timing constraints.
The internal bus monitor will assert the internal transfer error
acknowledge signal when TA response time is too long.
External bus cycles which are aborted by the M•CORE, still have the
address, R/W, TC[2:0], TSIZ[1:0], CS (if used), OE (reads only), and
SHS (if used) driven to the external pins.
While in emulation mode or master mode, special emulator chip-selects
(CSE[1:0]) are driven externally to allow internal/external accesses to be
tracked by external hardware See
In emulation mode, all port registers are mapped externally.
CSE[1:0] = 10 whenever any emulated port registers are addressed.
The lower bits of the address bus indicate the register accessed within
the block.
Accesses to the address space which contains the registers for the
internal modules (except ports) are indicated by CSE[1:0] = 11.
Internal accesses, other than to the specific module control registers, are
indicated by CSE[1:0] = 01. To emulate internal FLASH, the external
Freescale Semiconductor, Inc.
For More Information On This Product,
External Bus Interface Module (EBI)
Go to: www.freescale.com
Table
19-4.
MMC2107 – Rev. 2.0
MOTOROLA