MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 528

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chip Select Module
Technical Data
528
NOTE:
PS — Port Size Bit
WWS — Write Wait State Bit
WE — Write Enable Bit
The WE bit has no effect on the EB[3:0] pin function if the chip select is
not active. If the chip select is not active, the EB[3:0] pin function is byte
enable by default.
WS[2:0] — Wait States Field
read/write signal, which indicates whether the access is a read
(read/write = 1) or a write (read/write = 0). If the chip select logic
detects a violation (RO = 1 with read/write = 0), the access is ignored.
The PS bit defines the width of the external data port supported by the
chip select as either 16-bit or 32-bit. When a chip select is
programmed as a 16-bit port, the external device must be connected
to D[31:16]. For 32-bit accesses to 16-bit ports, the external memory
interface initiates two bus cycles and multiplexes data as needed to
complete the data transfer.
The WWS bit determines if an additional wait state is required for write
cycles. WWS does not affect read cycles.
The WE bit defines when the enable byte output pins (EB[3:0]) are
asserted. When WE is 0, EB[3:0] are configured as byte enables and
assert for both external read and external write accesses. When WE
is 1, EB[3:0] are configured as write enables and assert only for
external write accesses.
The WS field determines the number of wait states for the chip select
logic to insert before asserting the internal cycle termination signal.
One wait state is equal to one system clock cycle. If WS is configured
for zero wait states, then the internal cycle termination signal is
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Only read accesses allowed; write accesses ignored by the
0 = Read and write accesses allowed
1 = 32 bit port
0 = 16 bit port
1 = One additional wait state added for write cycles
0 = No additional wait state added for write cycles
1 = EB[3:0] configured as write enables
0 = EB[3:0] configured as byte enables
chip select logic
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Chip Select Module
MMC2107 – Rev. 2.0
MOTOROLA