MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 530

no-image

MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MMC2107CFCPV33
Manufacturer:
AMD
Quantity:
1 001
Part Number:
MMC2107CFCPV33
Manufacturer:
MOTOLOLA
Quantity:
745
Part Number:
MMC2107CFCPV33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MMC2107CFCPV33
Manufacturer:
MOT
Quantity:
2
Part Number:
MMC2107CFCPV33
Manufacturer:
FREESCALE
Quantity:
20 000
Chip Select Module
20.7 Functional Description
Technical Data
530
NOTE:
CSEN — Chip Select Enable Bit
Each chip select can provide a chip enable signal for an external device
and assert the internal bus cycle termination signal.
Setting the CSEN bit in CSCR enables the chip select to provide an
external chip enable.
Setting both the CSEN and TAEN bits in CSCR enables the chip select
to generate the internal bus cycle termination signal.
Both the chip select pin assertion and the bus cycle termination function
depend on an initial address/option match for activation. During the
matching process, the fixed base address of each chip select is
compared to the corresponding address for the bus cycle to determine
whether an address match has occurred. This match is further qualified
by comparing the internal read/write indication and access type with the
programmed values in CSCR of each chip select. When the address and
option information match the current cycle, the chip select is activated. If
no chip select matches the bus cycle information for the current access,
the chip select logic does not respond in any way.
Only one chip select can be active for a given bus cycle. The
configuration of the active chip select, determined by the wait state
(WS/WWS) field, the port size (PS) field, and the write enable (WE) field,
is used for the access.
WWS and WS are valid only if the TAEN bit is 1 for the active chip select.
When no chip select pin is available, the active chip select can still
terminate the bus cycle. If both the CSEN and TAEN bits are 1 and the
address/options match the chip select configuration, then the chip select
logic asserts the internal termination signal; the bus cycle terminates
after the programmed number of wait states. If the external TA or TEA
The CSEN bit enables the chip select logic. When the chip select
function is disabled, the CSx signal is negated high.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Chip select function enabled
0 = Chip select function disabled
Go to: www.freescale.com
Chip Select Module
MMC2107 – Rev. 2.0
MOTOROLA

Related parts for MMC2107CFCPV33