MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 535

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

21.2 Introduction
MMC2107 – Rev. 2.0
MOTOROLA
21.14.12.3
21.14.12.4
21.14.12.5
21.14.13 Instruction Address FIFO Buffer (PC FIFO) . . . . . . . . . . . 580
21.14.14 Reserved Test Control Registers . . . . . . . . . . . . . . . . . . .581
21.14.15 Serial Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
21.14.16 OnCE Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
21.14.17 Target Site Debug System Requirements . . . . . . . . . . . . 582
21.14.18 Interface Connector for JTAG/OnCE Serial Port . . . . . . . 582
The MMC2107 has two JTAG (Joint Test Action Group) TAP (test
access port) controllers:
At power-up, only the top-level TAP controller will be visible. If desired,
a user can then enable the low-level OnCE controller which will in turn
disable the top-level TAP controller. The top-level TAP controller will
remain disabled until either power is removed and reapplied to the
MMC2107 or until the test reset signal, TRST, is asserted (logic 0).
The OnCE TAP controller can be enabled in either of two ways:
Refer to
1. A top-level controller that allows access to the MMC2107’s
2. A low-level OnCE (on-chip emulation) controller that allows
1. With the top-level TAP controller in its test-logic-reset state:
2. Shift the ENABLE_MCU_ONCE instruction, 0x3, into the top-level
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boundary scan (external pins) register, IDCODE register, and
bypass register
access to MMC2107’s central processor unit (CPU) and
debugger-related registers
a. Deassert TRST, test reset (logic1)
b. Assert DE, the debug event (logic 0) for two TCLK, test clock,
TAP controller’s instruction register (IR) and pass through the TAP
controller state update-IR.
Figure
JTAG Test Access Port and OnCE
cycles
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Control State Register . . . . . . . . . . . . . . . . . . . . . . . . . 577
Writeback Bus Register . . . . . . . . . . . . . . . . . . . . . . . . 579
Processor Status Register . . . . . . . . . . . . . . . . . . . . . . 579
21-1.
JTAG Test Access Port and OnCE
Technical Data
Introduction
535