MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 537

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

21.3 Top-Level Test Access Port (TAP)
MMC2107 – Rev. 2.0
MOTOROLA
CAUTION:
The MMC2107 provides a dedicated user-accessible test access port
(TAP) that is fully compatible with the IEEE 1149.1 Standard Test
Access Port and Boundary-Scan Architecture. Problems associated with
testing high-density circuit boards have led to development of this
proposed standard under the sponsorship of the Test Technology
Committee of IEEE and the Joint Test Action Group (JTAG). The
MMC2107 implementation supports circuit-board test strategies based
on this standard.
The top-level TAP consists of five dedicated signal pins, a 16-state TAP
controller, an instruction register, and three data registers, a boundary
scan register for monitoring and controlling the device’s external pins, a
device identification register, and a 1-bit bypass (do nothing) register.
The top-level TAP provides the ability to:
Certain precautions must be observed to ensure that the top-level
TAP module does not interfere with non-test operation. See
21.10 Non-Scan Chain Operation
The MMC2107’s top-level TAP module includes a TAP controller, a 4-bit
instruction register, and three test data registers (a 1-bit bypass register,
a 200-bit boundary scan register, and a 32-bit IDCODE register). The
top-level tap controller and the low-level (OnCE) TAP controller share
the external signals described here.
1. Perform boundary scan (external pin) drive and monitor
2. Disable the MMC2107’s output pins
3. Read the MMC2107’s IDCODE device identification register
Freescale Semiconductor, Inc.
For More Information On This Product,
operations to test circuitry external to the MMC2107
JTAG Test Access Port and OnCE
Go to: www.freescale.com
for details.
JTAG Test Access Port and OnCE
Top-Level Test Access Port (TAP)
Technical Data
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