MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 543

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

21.5.3 SAMPLE/PRELOAD Instruction
21.5.4 ENABLE_MCU_ONCE Instruction
MMC2107 – Rev. 2.0
MOTOROLA
NOTE:
a logic 1. The remaining 31 bits are also set to fixed values on the rising
edge of TCLK following entry into the capture-DR state.
IDCODE is the default instruction placed into the instruction register
when the top-level TAP resets. Thus, after a TAP reset, the IDCODE
(data) register will be selected automatically.
The SAMPLE/PRELOAD instruction provides two separate functions.
First, it obtains a sample of the system data and control signals present
at the MMC2107 input pins and just prior to the boundary scan cell at the
output pins. This sampling occurs on the rising edge of TCLK in the
capture-DR state when an instruction encoding of hex 2 is resident in the
instruction register. The user can observe this sampled data by shifting
it through the boundary scan register to the output TDO by using the
shift-DR state. Both the data capture and the shift operation are
transparent to system operation.
The user is responsible for providing some form of external
synchronization to achieve meaningful results because there is no
internal synchronization between TCLK and the system clock.
The second function of the SAMPLE/PRELOAD instruction is to initialize
the boundary scan register update cells before selecting EXTEST or
CLAMP. This is achieved by ignoring the data being shifted out of the
TDO pin while shifting in initialization data. The update-DR state in
conjunction with the falling edge of TCLK can then transfer this data to
the update cells. This data will be applied to the external output pins
when EXTEST or CLAMP instruction is applied.
The ENABLE_MCU_ONCE is a public instruction to enable the
M•CORE OnCE TAP controller. When the OnCE TAP controller is
enabled, the top-level TAP controller connects the internal OnCE TDO
to the pin TDO and remains in the run-test/idle state. It will remain in this
state until TRST is asserted. While the OnCE TAP controller is enabled,
the top-level JTAG remains transparent.
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
JTAG Test Access Port and OnCE
Instruction Shift Register
Technical Data
543