MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 544

no-image

MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MMC2107CFCPV33
Manufacturer:
AMD
Quantity:
1 001
Part Number:
MMC2107CFCPV33
Manufacturer:
MOTOLOLA
Quantity:
745
Part Number:
MMC2107CFCPV33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MMC2107CFCPV33
Manufacturer:
MOT
Quantity:
2
Part Number:
MMC2107CFCPV33
Manufacturer:
FREESCALE
Quantity:
20 000
JTAG Test Access Port and OnCE
21.5.5 HIGHZ Instruction
21.5.6 CLAMP Instruction
21.5.7 BYPASS Instruction
Technical Data
544
The HIGHZ instruction is provided as a manufacturer’s optional public
instruction to prevent having to backdrive the output pins during
circuit-board testing. When HIGHZ is invoked, all output drivers,
including the 2-state drivers, are turned off (for example, high
impedance). The instruction selects the bypass register. HIGHZ also
asserts internal reset for the MMC2107 system logic to force a
predictable internal state.
The CLAMP instruction selects the bypass register and asserts internal
reset while simultaneously forcing all output pins and bidirectional pins
configured as outputs to the fixed values that are preloaded and held in
the boundary scan update register. This instruction enhances test
efficiency by reducing the overall shift path to a single bit (the bypass
register) while conducting an EXTEST type of instruction through the
boundary scan register.
The BYPASS instruction selects the single-bit bypass register, creating
a single-bit shift register path from the TDI pin to the bypass register to
the TDO pin. This instruction enhances test efficiency by reducing the
overall shift path when a device other than the MMC2107 processor
becomes the device under test on a board design with multiple chips on
the overall IEEE 1149.1 standard defined boundary scan chain. The
bypass register has been implemented in accordance with IEEE 1149.1
standard so that the shift register state is set to logic 0 on the rising edge
of TCLK following entry into the capture-DR state. Therefore, the first bit
to be shifted out after selecting the bypass register is always a logic 0 (to
differentiate a part that supports an IDCODE register from a part that
supports only the bypass register).
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA

Related parts for MMC2107CFCPV33