MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 546

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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JTAG Test Access Port and OnCE
21.7 Bypass Register
21.8 Boundary SCAN Register
21.9 Restrictions
Technical Data
546
The MMC2107 includes an IEEE 1149.1 standard-compliant bypass
register, which creates a single bit shift register path from TDI to the
bypass register to TDO when the BYPASS instruction is selected.
MMC2107 includes an IEEE 1149.1 standard-compliant boundary-scan
register. The boundary-scan register is connected between TDI and
TDO when the EXTEST or SAMPLE/PRELOAD instructions are
selected. This register captures signal pin data on the input pins, forces
fixed values on the output signal pins, and selects the direction and drive
characteristics (a logic value or high impedance) of the bidirectional and
three-state signal pins.
The test logic is implemented using static logic design, and TCLK can be
stopped in either a high or low state without loss of data. The system
logic, however, operates on a different system clock which is not
synchronized to TCLK internally. Any mixed operation requiring the use
of the IEEE 1149.1 standard test logic, in conjunction with system
functional logic that uses both clocks, must have coordination and
synchronization of these clocks done externally.
The control afforded by the output enable signals using the boundary
scan register and the EXTEST instruction requires a compatible
circuit-board test environment to avoid device-destructive
configurations. The user must avoid situations in which MMC2107
output drivers are enabled into actively driven networks.
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA

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