MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 549

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

MMC2107 – Rev. 2.0
MOTOROLA
Table 21-3
Bit
10
11
12
13
14
15
16
0
1
2
3
4
5
6
7
8
9
•
•
Freescale Semiconductor, Inc.
Table 21-3. Boundary-Scan Register Definition (Sheet 1 of 4)
For More Information On This Product,
The first column shows bit numbers assigned to each of the
register’s cells. The bit nearest to TDO (the first to be shifted in) is
defined as bit 0.
The second column lists the logical state bit for each MMC2107
pin alternately with the read/write direction control bit for that pin.
The logic state bits are non-inverting with respect to their
associated pins, so that a 1 logical state bit equates to a logical
high voltage on its corresponding pin. A direction control bit value
of 1 causes a pin’s logical state to be expressed by its logic state
bit, a read of a pin. A direction control bit value of 0 causes a pin’s
logical voltage to follow the state of its logical state bit, a write to a
pin.
D31 logical state
D31 direction control
A12 logical state
A12 direction control
A13 logical state
A13 direction control
A14 logical state
A14 direction control
A15 logical state
A15 direction control
A16 logical state
A16 direction control
A17 logical state
A17 direction control
CLKOUT logical state
CLKOUT direction control
A18 logical state
Logical State and Direction
Control Bits for Each Pin
JTAG Test Access Port and OnCE
defines the boundary-scan register.
Go to: www.freescale.com
(Note: Shaded regions indicate optional pins)
Bit
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
JTAG Test Access Port and OnCE
A18 direction control
A19 logical state
A19 direction control
RSTOUT logical state
RSTOUT direction control
A20 logical state
A20 direction control
RESET logical state
RESET direction control
A21 logical state
A21 direction control
A22 logical state
A22 direction control
TEA logical state
TEA direction control
EB0 logical state
EB0 direction control
Logical State and Direction
Control Bits for Each Pin
Boundary Scan
Technical Data
549