MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 560

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

JTAG Test Access Port and OnCE
21.14.3.2 CPU Debug Request (DBGRQ)
21.14.3.3 CPU Debug Acknowledge (DBGACK)
21.14.3.4 CPU Breakpoint Request (BRKRQ)
21.14.3.5 CPU Address, Attributes (ADDR, ATTR)
21.14.3.6 CPU Status (PSTAT)
21.14.3.7 OnCE Debug Output (DEBUG)
Technical Data
560
The DBGRQ signal is asserted by the OnCE control logic to request the
CPU to enter the debug state. It may be asserted for a number of
different conditions. Assertion of this signal causes the CPU to finish the
current instruction being executed, save the instruction pipeline
information, enter debug mode, and wait for further commands.
Asserting DBGRQ causes the device to exit stop, doze, or wait mode.
The CPU asserts the DBGACK signal upon entering the debug state.
This signal is part of the handshake mechanism between the OnCE
control logic and the CPU.
The BRKRQ signal is asserted by the OnCE control logic to signal that
a breakpoint condition has occurred for the current CPU bus access.
The CPU address and attribute information may be used in the memory
breakpoint logic to qualify memory breakpoints with access address and
cycle type information.
The trace logic uses the PSTAT signals to qualify trace count
decrements with specific CPU activity.
The DEBUG signal is used to indicate to on-chip resources that a debug
session is in progress. Peripherals and other units may use this signal to
modify normal operation for the duration of a debug session. This may
involve the CPU executing a sequence of instructions solely for the
purpose of visibility/system control. These instructions are not part of the
normal instruction stream that the CPU would have executed had it not
been placed in debug mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA