MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 561

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

21.14.4 OnCE Controller Registers
21.14.4.1 OnCE Command Register
MMC2107 – Rev. 2.0
MOTOROLA
This signal is asserted the first time the CPU enters the debug state and
remains asserted until the CPU is released by a write to the OnCE
command register with the GO and EX bits set, and a register specified
as either no register selected or the CPUSCR. This signal remains
asserted even though the CPU may enter and exit the debug state for
each instruction executed under control of the OnCE controller.
This section describes the OnCE controller registers:
All OnCE registers are addressed by means of the RS field in the OCMR,
as shown in
The OnCE command register (OCMR) is an 8-bit shift register that
receives its serial data from the TDI pin. This register corresponds to the
JTAG IR and is loaded when the update-IR TAP controller state is
entered. It holds the 8-bit commands shifted in during the shift-IR
controller state to be used as input for the OnCE decoder. The OCMR
contains fields for controlling access to a OnCE resource, as well as
controlling single-step operation, and exit from OnCE mode.
Although the OCMR is updated during the update-IR TAP controller
state, the corresponding resource is accessed in the DR scan sequence
of the TAP controller, and as such, the update-DR state must be
transitioned through in order for an access to occur. In addition, the
update-DR state must also be transitioned through in order for the
single-step and/or exit functionality to be performed, even though the
command appears to have no data resource requirement associated
with it.
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Freescale Semiconductor, Inc.
For More Information On This Product,
OnCE command register (OCMR)
OnCE control register (OCR)
OnCE status register (OSR)
JTAG Test Access Port and OnCE
Go to: www.freescale.com
Table
21-4.
JTAG Test Access Port and OnCE
Functional Description
Technical Data
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