MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 562

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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JTAG Test Access Port and OnCE
Technical Data
562
R/W — Read/Write Bit
GO — Go Bit
EX — Exit Bit
RS4–RS0 — Register Select Field
When the GO bit is set, the device executes the instruction in the IR
register in the CPUSCR. To execute the instruction, the processor
leaves debug mode, executes the instruction, and if the EX bit is
cleared, returns to debug mode immediately after executing the
instruction. The processor resumes normal operation if the EX bit is
set. The GO command is executed only if the operation is a read/write
to either the CPUSCR or to “no register selected.” Otherwise, the GO
bit has no effect. The processor leaves debug mode after the TAP
controller update-DR state is entered.
When the EX bit is set, the processor leaves debug mode and
resumes normal operation until another debug request is generated.
The exit command is executed only if the GO bit is set and the
operation is a read/write to the CPUSCR or a read/write to “no register
selected.” Otherwise, the EX bit has no effect. The processor exits
debug mode after the TAP controller update-DR state is entered.
The RS field defines the source for the read operation or the
destination for the write operation.
addresses.
Freescale Semiconductor, Inc.
Bit 7
R/W
For More Information On This Product,
1 = Read the data in the register specified by the RS field.
0 = Write the data associated with the command into the register
1 = Execute instruction in IR
0 = Inactive (no action taken)
1 = Leave debug mode
0 = Remain in debug mode
JTAG Test Access Port and OnCE
specified by the RS field.
Figure 21-8. OnCE Command Register (OCMR)
Go to: www.freescale.com
G
6
EX
5
RS4
4
Table 21-4
RS3
3
RS2
2
shows OnCE register
MMC2107 – Rev. 2.0
RS1
1
MOTOROLA
Bit 0
RS0

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