MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 568

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

JTAG Test Access Port and OnCE
21.14.4.3 OnCE Status Register
Technical Data
568
Reset:
Reset:
Read:
Read:
Write:
Write:
The 16-bit OnCE status register (OSR) indicates the reason(s) that
debug mode was entered and the current operating mode of the CPU.
HDRO — Hardware Debug Request Occurrence Flag
DRO — Debug Request Occurrence Flag
MBO — Memory Breakpoint Occurrence Flag
HDRO is set when the processor enters debug mode as a result of a
hardware debug request from the IDR signal or the DE pin. This bit is
cleared on test logic reset or when debug mode is exited with the GO
and EX bits set.
DRO is set when the processor enters debug mode and the debug
request (DR) control bit in the OnCE control register is set. This bit is
cleared on test logic reset or when debug mode is exited with the GO
and EX bits set.
MBO is set when a memory breakpoint request has been issued to
the CPU via the BRKRQ input and the CPU enters debug mode. In
some situations involving breakpoint requests on instruction
prefetches, the CPU may discard the request along with the prefetch.
In this case, this bit may become set due to the CPU entering debug
mode for another reason. This bit is cleared on test logic reset or
when debug mode is exited with the GO and EX bits set.
Freescale Semiconductor, Inc.
For More Information On This Product,
Bit 15
MBO
Bit 7
0
0
JTAG Test Access Port and OnCE
Figure 21-10. OnCE Status Register (OSR)
Go to: www.freescale.com
= Unimplemented or reserved
SWO
14
0
6
0
TO
13
0
5
0
FRZO
12
0
4
0
SQB
11
0
3
0
SQA
10
0
2
0
MMC2107 – Rev. 2.0
HDRO
PM1
9
0
1
0
MOTOROLA
DRO
PM0
Bit 8
Bit 0
0
0