MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 574

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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JTAG Test Access Port and OnCE
21.14.8.2 Trace Operation
21.14.9 Methods of Entering Debug Mode
21.14.9.1 Debug Request During RESET
Technical Data
574
To initiate trace mode operation:
When debug mode is exited, the counter is decremented after each
execution of an instruction. Interrupts can be serviced, and all
instructions executed (including interrupt services) will decrement the
trace counter.
When the trace counter decrements to zero, the OnCE control logic
requests that the processor re-enter debug mode, and the trace
occurrence bit TO in the OSR is set to indicate that debug mode has
been requested as a result of the trace count function. The trace counter
allows a minimum of two instructions to be specified for execution prior
to entering trace (specified by a count value of one), unless sequential
breakpoint control operation is enabled in the OCR. In this case, a value
of zero (indicating a single instruction) is allowed.
The PM status field in the OSR indicates that the CPU has entered
debug mode. The following paragraphs discuss conditions that invoke
debug mode.
When the DR bit in the OCR is set, assertion of RESET causes the
device to enter debug mode. In this case the device may fetch the reset
1. Load the OTC register with a value. This value must be non-zero,
2. Initialize the program counter and instruction register in the
3. Set the TME bit in the OCR.
4. Release the processor from debug mode by executing the
Freescale Semiconductor, Inc.
For More Information On This Product,
unless sequential breakpoint control operation is enabled in the
OCR register. In this case, a value of zero (indicating a single
instruction) is allowed.
CPUSCR with values corresponding to the start location of the
instruction(s) to be executed real-time.
appropriate command issued by the external command controller.
JTAG Test Access Port and OnCE
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA

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