MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 575

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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21.14.9.2 Debug Request During Normal Activity
21.14.9.3 Debug Request During Stop, Doze, or Wait Mode
21.14.9.4 Software Request During Normal Activity
21.14.10 Enabling OnCE Trace Mode
MMC2107 – Rev. 2.0
MOTOROLA
NOTE:
vector and the first instruction of the reset exception handler but does not
execute an instruction before entering debug mode.
Setting the DR bit in the OCR during normal device activity causes the
device to finish the execution of the current instruction and then enter
debug mode. Note that in this case the device completes the execution
of the current instruction and stops after the newly fetched instruction
enters the CPU instruction latch. This process is the same for any newly
fetched instruction, including instructions fetched by interrupt processing
or those that will be aborted by interrupt processing.
Setting the DR bit in the OCR when the device is in stop, doze, or wait
mode (for instance, after execution of a STOP, DOZE, or WAIT
instruction) causes the device to exit the low-power state and enter the
debug mode. Note that in this case, the device completes the execution
of the STOP, DOZE, or WAIT instruction and halts after the next
instruction enters the instruction latch.
Executing the BKPT instruction when the FDB (force debug enable
mode) control bit in the control state register is set causes the CPU to
enter debug mode after the instruction following the BKPT instruction
has entered the instruction latch.
When the OnCE trace mode mechanism is enabled and the trace count
is greater than zero, the trace counter is decremented for each
instruction executed. Completing execution of an instruction when the
trace counter is zero causes the CPU to enter debug mode.
Only instructions actually executed cause the trace counter to
decrement. An aborted instruction does not decrement the trace counter
and does not invoke debug mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
JTAG Test Access Port and OnCE
Functional Description
Technical Data
575

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