MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 578

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

JTAG Test Access Port and OnCE
Technical Data
578
Reset:
Reset:
Read:
Read:
Write:
Write:
Reserved bits represent the internal processor state. Restore these bits
to their original value after a debug session is completed, for example,
when a OnCE command is issued with the GO and EX bits set and not
ignored. Set these bits to 1s while instructions are executed during a
debug session.
FFY — Feed Forward Y Operand Bit
FDB — Force Debug Enable Mode Bit
SZ1 and SZ0 — Prefetch Size Field
This control bit is used to force the content of the WBBR to be used
as the Y operand value of the first instruction to be executed following
an update of the CPUSCR. This gives the debug firmware the
capability of updating processor registers by initializing the WBBR
with the desired value, setting the FFY bit, and executing a MOV
instruction to the desired register.
Setting this control bit places the processor in debug enable mode. In
debug enable mode, execution of the BKPT instruction as well as
recognition of the BRKRQ input causes the processor to enter debug
mode, as if the DBGRQ input had been asserted.
This control field is used to drive the CPU SIZ1 and SIZ0 outputs on
the first instruction pre-fetch caused by issuing a OnCE command
with the GO bit set and not ignored. It should be set to indicate a 16-bit
size, for example, 0b10. This field should be restored to its original
value after a debug session is completed, for example, when a OnCE
command is issued with the GO and EX bits set and not ignored.
Freescale Semiconductor, Inc.
For More Information On This Product,
RSVD
Bit 15
Bit 7
FDB
0
JTAG Test Access Port and OnCE
Figure 21-14. Control State Register (CTL)
Go to: www.freescale.com
RSVD
SZ1
14
6
0
RSVD
SZ0
13
5
0
RSVD
TC2
12
4
0
RSVD
TC1
11
3
0
RSVD
TC0
10
2
0
MMC2107 – Rev. 2.0
RSVD
RSVD
9
1
MOTOROLA
RSVD
Bit 8
FFY
Bit 0
0