MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 605

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

22.14 OnCE, JTAG, and Boundary Scan Timing
MMC2107 – Rev. 2.0
MOTOROLA
No.
1. Parameters 9 and 10 apply to the DE pin when used to enable OnCE. Parameters 15 and 16 apply to the DE pin when
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
used to request the processor to enter debug mode.
TCLK frequency of operation
TCLK cycle period
TCLK clock pulse width
TCLK rise and fall times
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low-to-boundary scan output data valid
TCLK low-to-boundary scan output high Z
TMS, TDI, and DE input data setup time to TCLK rise
TMS, TDI, and DE input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high Z
TRST assert time
TRST setup time (negation) to TCLK high
DE input data setup time to CLKOUT rise
DE input data hold time after CLKOUT rise
CLKOUT high to DE data valid
CLKOUT high to DE high Z
TCLK INPUT
Table 22-14. OnCE, JTAG, and Boundary Scan Timing
Characteristics
(V
Freescale Semiconductor, Inc.
DD
Figure 22-9. Test Clock Input Timing
For More Information On This Product,
4
= 2.7 to 3.6 V, V
V
IH
Go to: www.freescale.com
V
Electrical Specifications
IL
(1)
(1)
3
SS
= 0 V, T
(1)
4
(1)
2
Symbol
t
t
t
t
t
t
t
t
t
A
t
TAPDST
TAPDHT
TRSTAT
TRSTST
TDODV
t
f
t
BSDST
BSDHT
t
t
TDODZ
DEDST
DEDHT
t
t
t
BSDV
DEDV
DEDZ
JCYC
JCYC
BSDZ
JCRF
JCW
= T
OnCE, JTAG, and Boundary Scan Timing
L
to T
3
H
Min
100
25
24
15
10
10
dc
)
2
0
5
0
0
7
0
0
2
0
0
Electrical Specifications
1/2 x f
Max
40
40
25
20
10
—
—
—
—
—
—
—
—
—
—
3
9
sys
Technical Data
MHz
Unit
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
605