MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 95

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

MMC2107 – Rev. 2.0
MOTOROLA
LOAD — Pad Driver Load Bit
SHEN — Show Cycle Enable Bit
EMINT — Emulate Internal Address Space Bit
MODE[2:0] — Chip Configuration Mode Field
The LOAD bit selects full or default drive strength for selected pad
output drivers. For maximum capacitive load, set the LOAD bit to
select full drive strength. For reduced power consumption, clear the
LOAD bit to select default drive strength.
Table 3-2
The SHEN bit enables the external memory interface to drive the
external bus during internal transfer operations.
In emulation mode, the SHEN bit is read-only. In all other modes, it is
a read/write bit.
The EMINT bit enables chip select 1 (CS1) to decode the internal
memory address space.
The EMINT bit is read-always but can be written only in emulation
mode.
This read-only field reflects the chip configuration mode, as shown in
Table
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1 = Full drive strength
0 = Default drive strength
1 = Show cycles enabled
0 = Show cycles disabled
1 = CS1 decodes internal memory address space.
0 = CS1 decodes external memory address space.
3-4.
Chip Configuration Module (CCM)
Table 3-4. Chip Configuration Mode Selection
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shows the read/write accessibility of this write-once bit.
MODE[2:0]
10X
0XX
111
110
Master mode
Single-chip mode
FAST mode
Emulation mode
Chip Configuration Mode
Chip Configuration Module (CCM)
Memory Map and Registers
Technical Data
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