MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 139

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

VRS7–VRS4 — VCO Range Select Bits
10.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU
interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL)
enables CPU interrupt requests from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether
CPU interrupt requests are enabled or not. When the AUTO bit is clear, CPU interrupt requests from the
PLL are disabled and PLLF reads as logic 0.
Software should read the LOCK bit after a PLL CPU interrupt request to see if the request was due to an
entry into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two
can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO
clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency
sensitive, CPU interrupt requests should be disabled to prevent PLL interrupt service routines from
impeding software performance or from exceeding stack limitations.
Freescale Semiconductor
These read/write bits control the hardware center-of-range linear multiplier L, which controls the
hardware center-of-range frequency, f
10.5.1 PLL Control
register (PCTL) is set. See
select bits disables the PLL and clears the BCS bit in the PCTL. (See
Circuit
to $6 to give a default range multiply value of 6.
and
10.3.2.5 Special Programming Exceptions
The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
The VCO range select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1) and prevents selection of the
VCO clock as the source of the base clock (BCS = 1) if the VCO range
select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
MUL7:MUL6:MUL5:MUL4
Register.) VRS7–VRS4 cannot be written when the PLLON bit in the PLL control
Table 10-3. VCO Frequency Multiplier (N) Selection
0000
0001
0010
0011
1101
1110
1111
10.3.2.5 Special Programming
VRS
. (See
NOTE
NOTE
10.3.2.1
VCO Frequency Multiplier (N)
for more information.) Reset initializes the bits
Circuits,
Exceptions. A value of $0 in the VCO range
10.3.2.4 Programming the
13
14
15
1
1
2
3
10.3.3 Base Clock Selector
PLL, and
Interrupts
139