MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 167

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MC908AZ60ACFU

Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908AZ60ACFU

Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Chapter 16
Low-Voltage Inhibit (LVI)
16.1 Introduction
This chapter describes the low-voltage inhibit module (LVI47, Version A), which monitors the voltage on
the V
16.2 Features
Features of the LVI module include:
16.3 Functional Description
Figure 16-1
contains a bandgap reference circuit and comparator. The LVI power bit, LVIPWR, enables the LVI to
monitor V
falls below a voltage, LVI
cycles.
Note that short V
within the specified operating voltage range if normal microcontroller operation is to be guaranteed.
LVISTOP, enables the LVI module during stop mode. This will ensure when the STOP instruction is
implemented, the LVI will continue to monitor the voltage level on V
are in the configuration register, CONFIG-1 (see
Once an LVI reset occurs, the MCU remains in reset until V
be above LVI
Operation). The output of the comparator controls the state of the LVIOUT flag in the LVI status register
(LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
Freescale Semiconductor
DD
Programmable LVI Reset
Programmable Power Consumption
Digital Filtering of V
pin and can force a reset when the V
DD
shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate a reset when V
TRIPR
If a low voltage interrupt (LVI) occurs during programming of EEPROM or
Flash memory, then adequate programming time may not have been
allowed to ensure the integrity and retention of the data. It is the
responsibility of the user to ensure that in the event of an LVI any addresses
being programmed receive specification programming conditions.
DD
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
for only one CPU cycle to bring the MCU out of reset (see
spikes may not trip the LVI. It is the user’s responsibility to ensure a clean V
TRIPF
DD
Pin Level
, and remains at or below that level for nine or more consecutive CPU
DD
voltage falls to the LVI trip voltage.
NOTE
Chapter 11 Configuration Register
DD
rises above a voltage, LVI
DD
. LVIPWR, LVISTOP, and LVIRST
16.3.2 Forced Reset
(CONFIG-1)).
TRIPR
. V
DD
DD
signal
must
DD
167

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