MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 231

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

20.3.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIMB can generate a PWM
signal. The value in the TIMB counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIMB counter modulo registers. The time
between overflows is the period of the PWM signal.
As
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMB
to clear the channel pin on output compare if the polarity of the PWM pulse is 1. Program the TIMB to set
the pin if the polarity of the PWM pulse is 0.
The value in the TIMB counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMB counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is $000 (see
The value in the TIMB channel registers determines the pulse width of the PWM output. The pulse width
of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMB channel registers
produces a duty cycle of 128/256 or 50%.
20.3.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in
Modulation
pulse width value over the value currently in the TIMB channel registers.
An unsynchronized write to the TIMB channel registers to change a pulse width value could cause
incorrect operation for up to two PWM periods. For example, writing a new value before the counter
reaches the old value but after the counter reaches the new value prevents any compare during that PWM
period. Also, using a TIMB overflow interrupt routine to write a new, smaller pulse width value may cause
the compare to be missed. The TIMB may pass the new value before it is written to the TIMB channel
registers.
Freescale Semiconductor
Figure 20-3
(PWM). The pulses are unbuffered because changing the pulse width requires writing the new
PTEx/TCHx
shows, the output compare value in the TIMB channel registers determines the pulse width
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
OVERFLOW
Figure 20-3. PWM Period and Pulse Width
PULSE
WIDTH
PERIOD
COMPARE
OUTPUT
OVERFLOW
20.8.1 TIMB Status and Control
COMPARE
OUTPUT
OVERFLOW
COMPARE
Functional Description
OUTPUT
20.3.4 Pulse Width
Register).
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