MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 239

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
MSxB — Mode Select Bit B
MSxA — Mode Select Bit A
Freescale Semiconductor
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIMB counter registers matches the value in the TIMB channel x registers.
When CHxIE = 1, clear CHxF by reading TIMB channel x status and control register with CHxF set,
and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due
to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
This read/write bit enables TIMB CPU interrupts on channel x.
Reset clears the CHxIE bit.
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMB
channel 0.
Setting MS0B disables the channel 1 status and control register and reverts TBCH1 to
general-purpose I/O.
Reset clears the MSxB bit.
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation (see
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
Register Name and Address
Register Name and Address
Figure 20-7. TIMB Channel Status and Control Registers (TBSC0–TBSC1)
Reset:
Reset:
Read:
Read:
Write:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
CH0F
CH1F
Bit 7
Bit 7
R
0
0
0
0
= Reserved
CH0IE
CH1IE
Table
6
0
6
0
TBSC0 — $0045
TBSC1 — $0048
20-2).
MS0B
5
0
5
0
R
0
MS0A
MS1A
4
0
4
0
ELS0B
ELS1B
3
0
3
0
ELS0A
ELS1A
2
0
2
0
TOV0
TOV1
1
0
1
0
CH0MAX
CH1MAX
Bit 0
Bit 0
0
0
I/O Registers
239