MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 263

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MC908AZ60ACFU

Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908AZ60ACFU

Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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22.8 Port G
Port G is a 3-bit special function port that shares all of its pins with the keyboard interrupt module (KBD).
Note that Port G is only available on 64-pin package options.
22.8.1 Port G Data Register
The port G data register contains a data latch for each of the three port G pins.
PTG[2:0] — Port G Data Bits
KBD[2:0] — Keyboard Wakeup pins
22.8.2 Data Direction Register G
Data direction register G determines whether each port G pin is an input or an output. Writing a logic 1 to
a DDRG bit enables the output buffer for the corresponding port G pin; a logic 0 disables the output buffer.
Freescale Semiconductor
These read/write bits are software programmable. Data direction of each port G pin is under the control
of the corresponding bit in data direction register G. Reset has no effect on PTG[2:0].
The keyboard interrupt enable bits, KBIE[2:0], in the keyboard interrupt control register, enable the port
G pins as external interrupt pins (See
interrupt pin will override the corresponding DDRGx.
Alternative
Function:
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
$000A
$000E
Bit 7
Bit 7
R
R
R
R
0
0
0
Figure 22-21. Data Direction Register G (DDRG)
Figure 22-20. Port G Data Register (PTG)
= Reserved
= Reserved
R
R
6
0
6
0
0
Chapter 24 Keyboard Module
R
R
5
0
5
0
0
Unaffected by Reset
R
R
4
0
4
0
0
R
R
3
0
3
0
0
DDRG2
PTG2
KBD2
2
2
0
(KBI)). Enabling an external
DDRG1
PTG1
KBD1
1
1
0
DDRG0
PTG0
KBD0
Bit 0
Bit 0
0
Port G
263

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