MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 329

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Interrupts
26.3.2 Voltage Conversion
When the input voltage to the ADC equals V
(see
28.1.6 ADC
Characteristics), the ADC converts the
REFH
signal to $FF (full scale). If the input voltage equals V
the ADC converts it to $00. Input voltages
SSA,
between V
and V
are a straight-line linear conversion. Conversion accuracy of all other input
REFH
SSA
voltages is not guaranteed. Avoid current injection on unused ADC inputs to prevent potential conversion
error.
NOTE
Input voltage should not exceed the analog supply voltages.
26.3.3 Conversion Time
Conversion starts after a write to the ADSCR (ADC status control register, $0038), and requires between
16 and 17 ADC clock cycles to complete. Conversion time in terms of the number of bus cycles is a
function of ADICLK select, CGMXCLK frequency, bus frequency, and ADIV prescaler bits. For example,
with a CGMXCLK frequency of 4 MHz, bus frequency of 8 MHz, and fixed ADC clock frequency of 1 MHz,
one conversion will take between 16 and 17 μs and there will be between 128 bus cycles between each
conversion. Sample rate is approximately 60 kHz.
Refer to
28.1.6 ADC
Characteristics.
16 to 17 ADC Clock Cycles
Conversion Time = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
ADC Clock Frequency
Number of Bus Cycles = Conversion Time x Bus Frequency
26.3.4 Continuous Conversion
In the continuous conversion mode, the ADC data register will be filled with new data after each
conversion. Data from the previous conversion will be overwritten whether that data has been read or not.
Conversions will continue until the ADCO bit (ADC status control register, $0038) is cleared. The COCO
bit is set after the first conversion and will stay set for the next several conversions until the next write of
the ADC status and control register or the next read of the ADC data register.
26.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes. See
28.1.6 ADC Characteristics
for
accuracy information.
26.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. A CPU interrupt is generated if the COCO bit (ADC status control register, $0038) is at logic 0.
The COCO bit is not used as a conversion complete flag when interrupts are enabled.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
329