MCF5307FT66B Freescale Semiconductor, MCF5307FT66B Datasheet - Page 66
MCF5307FT66B
Manufacturer Part Number
MCF5307FT66B
Description
IC MPU 32BIT COLDF 66MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307FT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Programming Model
On-chip breakpoint resources include the following:
These registers can be accessed through the dedicated debug serial communication channel,
or from the processor’s supervisor programming model, using the WDEBUG instruction.
The enhancements of the Revision B debug specification are fully backward-compatible
with the A revision. For more information, see Chapter 5, “Debug Support.”
2.2 Programming Model
The MCF5307 programming model consists of three instruction and register groups—user,
MAC (also user-mode), and supervisor, shown in Figure 2-2. User mode programs are
restricted to user and MAC instructions and programming models. Supervisor-mode
system software can reference all user-mode and MAC instructions and registers and
additional supervisor instructions and control registers. The user or supervisor
programming model is selected based on SR[S]. The following sections describe the
registers in the user, MAC, and supervisor programming models.
2-26
• Configuration/status register (CSR)
• Background debug mode (BDM) address attributes register (BAAR)
• Bus attributes and mask register (AATR)
• Breakpoint registers. These can be used to define triggers combining address, data,
• Data breakpoint mask register (DBMR)
• Trigger definition register (TDR) can be programmed to generate a processor halt or
and PC conditions in single- or dual-level definitions. They include the following:
— PC breakpoint register (PBR)
— PC breakpoint mask register (PBMR)
— Data operand address breakpoint registers (ABHR/ABLR)
— Data breakpoint register (DBR)
initiate a debug interrupt exception.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MCF5307 User’s Manual
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