MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 579
MPC564CZP40
Manufacturer Part Number
MPC564CZP40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564CZP40
Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC564CZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Therefore, conversion time requires a minimum of 14 QCLK clocks (seven µs with a 2.0-MHz QCLK). If
the maximum final sample time period of 8 QCLKs is selected, the total conversion time is 20 QCLKs (10
µs with a 2.0-MHz QCLK)
Figure 14-21
14.3.12 Channel Decode and Multiplexer
The internal multiplexer selects one of the 16 analog input signals for conversion. The selected input is
connected to the sample buffer amplifier. The multiplexer also includes positive and negative stress
protection circuitry, which prevents deselected channels from affecting the selected channel when current
is injected into the deselected channels. Refer to
current levels.
14.3.13 Sample Buffer Amplifier
The sample buffer is used to raise the effective input impedance of the A/D converter, so that external
components (higher bandwidth or higher impedance) are less critical to accuracy. The input voltage is
buffered onto the sample capacitor to reduce crosstalk between channels.
14.3.14 Digital to Analog Converter (DAC) Array
The digital to analog converter (DAC) array consists of binary-weighted capacitors and a resistor-divider
chain. The reference voltages, V
DAC also converts the following three internal channels:
The DAC array serves to provide a mechanism for the successive approximation A/D conversion.
Freescale Semiconductor
•
•
•
QCLK
V
V
(V
RH
RL
RH
— Reference voltage low
— Reference voltage high
– V
illustrates the timing for conversions.
RL
)/2 — Reference voltage
RH
“Buffer”
2 cycles
Sample
MPC561/MPC563 Reference Manual, Rev. 1.2
Time
Sample Time
and V
Figure 14-21. Conversion Timing
RL
“Final” Sample
N cycles:
(2 or 8)
, are used by the DAC to perform ratiometric conversions. The
Time
Appendix F, “Electrical
Successive Approximation Resolution
Sequence
Resolution (“Conv”)
10 cycles
Time
Characteristics,” for specific
QADC64E Enhanced Mode Operation
14-37
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