MC68HC908GR8CDW Freescale Semiconductor, MC68HC908GR8CDW Datasheet - Page 131

• Manufacturer Part Number: MC68HC908GR8CDW
• Description: IC MCU 8K FLASH 8MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GR8CDW

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 17
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MC68HC908GR8 — Rev 4.0
MOTOROLA
OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit
SCIBDSRC — SCI Baud Rate Clock Source Bit
COPRS — COP Rate Select Bit
LVISTOP — LVI Enable in Stop Mode Bit
LVIRSTD — LVI Reset Disable Bit
LVIPWRD — LVI Power Disable Bit
Freescale Semiconductor, Inc.
OSCSTOPENB enables the oscillator to continue operating during stop
mode. Setting the OSCSTOPENB bit allows the oscillator to operate
continuously even during stop mode. This is useful for driving the
timebase module to allow it to generate periodic wakeup while in stop
mode. (See
SCIBDSRC controls the clock source used for the SCI. The setting of
this bit affects the frequency at which the SCI operates.
COPRS selects the COP timeout period. Reset clears COPRS. See
Computer Operating Properly
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP. See
Mode.
LVIRSTD disables the reset signal from the LVI module. See
Voltage Inhibit
LVIPWRD disables the LVI module. See
For More Information On This Product,
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
1 = Internal data bus clock used as clock source for SCI
0 = External oscillator used as clock source for SCI
1 = COP timeout period = 2
0 = COP timeout period = 2
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
1 = LVI module resets disabled
0 = LVI module resets enabled
1 = LVI module power disabled
0 = LVI module power enabled
Configuration Register (CONFIG)
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Clock Generator Module (CGM)
(LVI).
(COP).
13
18
– 2
– 2
4
4
CGMXCLK cycles
CGMXCLK cycles
Configuration Register (CONFIG)
Low-Voltage Inhibit
subsection
Functional Description
Stop
Technical Data
Mode.)
(LVI).
Low-
Stop
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