MC68HC908GR8CDW Freescale Semiconductor, MC68HC908GR8CDW Datasheet - Page 52
MC68HC908GR8CDW
Manufacturer Part Number
MC68HC908GR8CDW
Description
IC MCU 8K FLASH 8MHZ 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908GR4CFAE.pdf
(408 pages)
Specifications of MC68HC908GR8CDW
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
17
Program Memory Size
7.5KB (7.5K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Low Power Modes
3.6 Clock Generator Module (CGM)
3.6.1 Wait Mode
3.6.2 Stop Mode
3.7 Computer Operating Properly Module (COP)
3.7.1 Wait Mode
Technical Data
52
The CGM remains active in wait mode. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
If the OSCSTOPEN bit in the CONFIG register is cleared (default), then
the STOP instruction disables the CGM (oscillator and phase-locked
loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
If the OSCSTOPEN bit in the CONFIG register is set, then the phase
locked loop is shut off, but the oscillator will continue to operate in stop
mode.
The COP remains active in wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine
or a DMA service routine.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Low Power Modes
MC68HC908GR8 — Rev 4.0
MOTOROLA
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