MC68HC908LJ24CPK Freescale Semiconductor, MC68HC908LJ24CPK Datasheet - Page 294
MC68HC908LJ24CPK
Manufacturer Part Number
MC68HC908LJ24CPK
Description
IC MCU 24K FLASH 8MHZ SPI 80LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908LK24CFUE.pdf
(464 pages)
Specifications of MC68HC908LJ24CPK
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
48
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MC68HC908LJ24CPK
Manufacturer:
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Serial Peripheral Interface Module (SPI)
14.6.2 Transmission Format When CPHA = 0
Data Sheet
294
NOTE:
The clock phase (CPHA) control bit selects one of two fundamentally
different transmission formats. The clock phase and polarity should be
identical for the master SPI device and the communicating slave device.
In some cases, the phase and polarity are changed between
transmissions to allow a master device to communicate with peripheral
slaves having different requirements.
Before writing to the CPOL bit or the CPHA bit, disable the SPI by
clearing the SPI enable bit (SPE).
Figure 14-4
figure should not be used as a replacement for data sheet parametric
information.
Two waveforms are shown for SPSCK: one for CPOL = 0 and another
for CPOL = 1. The diagram may be interpreted as a master or slave
timing diagram since the serial clock (SPSCK), master in/slave out
(MISO), and master out/slave in (MOSI) pins are directly connected
between the master and the slave. The MISO signal is the output from
the slave, and the MOSI signal is the output from the master. The SS line
is the slave select input to the slave. The slave SPI drives its MISO
output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See
edge is the MSB capture strobe. Therefore, the slave must begin driving
its data before the first SPSCK edge, and a falling edge on the SS pin is
used to start the slave data transmission. The slave’s SS pin must be
toggled back to high and then low again between each byte transmitted
as shown in
Serial Peripheral Interface Module (SPI)
14.8.2 Mode Fault
Figure
shows an SPI transmission in which CPHA is logic 0. The
14-5.
Error.) When CPHA = 0, the first SPSCK
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
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