MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 211

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8.5.4 I
This I2SR contains bits that indicate transaction direction and status.
Table 8-5 describes I2SR fields.
7
6
5
4
3
2
1
0
Bits
ICF
IAAS
IBB
IAL
—
SRW
IIF
RXAK
Name
Address
2
Reset
Field
C Status Register (I2SR)
R/W
0 Transfer in progress
1 Transfer complete. Set by the falling edge of the ninth clock of a byte transfer.
SRW and set its TX/RX mode accordingly. Writing to I2CR clears this bit.
0 Not addressed.
1 Addressed as a slave. Set when its own address (IADR) matches the calling address.
0 Bus is idle. If a STOP signal is detected, IBB is cleared.
1 Bus is busy. When START is detected, IBB is set.
writing zero to it.)
Reserved, should be cleared.
address sent from the master. SRW is valid only when a complete transfer has occurred, no other
transfers have been initiated, and the I
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
0 No I
1 An interrupt is pending, which causes a processor interrupt request (if IIEN = 1). Set when one of
Received acknowledge. The value of SDA during the acknowledge bit of a bus cycle.
0 An acknowledge signal was received after the completion of 8-bit data transmission on the bus
1 No acknowledge signal was detected at the ninth clock.
Data transferring bit. While one byte of data is transferred, ICF is cleared.
I
I
Arbitration lost. Set by hardware in the following circumstances. (IAL must be cleared by software by
Slave read/write. When IAAS is set, SRW indicates the value of the R/W command bit of the calling
I
2
2
2
C addressed as a slave bit. The CPU is interrupted if I2CR[IIEN] is set. Next, the CPU must check
C bus busy bit. Indicates the status of the bus.
C interrupt. Must be cleared by software by writing a zero to it in the interrupt routine.
• SDA sampled low when the master drives high during an address or data-transmit cycle.
• SDA sampled low when the master drives high during the acknowledge bit of a data-receive
• A start cycle is attempted when the bus is busy.
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not request it.
• Complete one byte transfer (set at the falling edge of the ninth clock)
• Reception of a calling address that matches its own specific address in slave-receive mode
• Arbitration lost
the following occurs:
cycle.
ICF
2
7
C interrupt pending
Freescale Semiconductor, Inc.
Figure 8-8. I
For More Information On This Product,
IAAS
Table 8-5. I2SR Field Descriptions
R
6
Go to: www.freescale.com
Chapter 8. I
IBB
5
2
CR Status Register (I2SR)
R/W
MBAR + 0x28C
2
IAL
C module is a slave and has an address match.
4
1000_0001
2
C Module
Description
—
3
R
SRW
2
R/W
IIF
1
Programming Model
RXAK
R
0
8-9