MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 24

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure
Number
18-19
18-20
18-21
18-22
18-23
18-24
18-25
18-26
18-27
18-28
18-29
18-30
18-31
18-32
18-33
18-34
19-1
19-2
19-4
19-5
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
xxiv
Longword Read from an 8-Bit Port, External Termination...................................... 18-16
Longword Read from an 8-Bit Port, Internal Termination ....................................... 18-16
Example of a Misaligned Longword Transfer (32-Bit Port) .................................... 18-17
Example of a Misaligned Word Transfer (32-Bit Port) ............................................ 18-17
Interrupt-Acknowledge Cycle Flowchart ................................................................. 18-20
Basic No-Wait-State External Master Access .......................................................... 18-22
External Master Burst Line Access to 32-Bit Port.................................................... 18-24
MCF5307 Two-Wire Mode Bus Arbitration Interface............................................. 18-25
Two-Wire Bus Arbitration with Bus Request Asserted............................................ 18-26
Two-Wire Implicit and Explicit Bus Mastership...................................................... 18-27
MCF5307 Two-Wire Bus Arbitration Protocol State Diagram................................ 18-28
Three-Wire Implicit and Explicit Bus Mastership.................................................... 18-30
Three-Wire Bus Arbitration...................................................................................... 18-31
Three-Wire Bus Arbitration Protocol State Diagram ............................................... 18-32
Master Reset Timing................................................................................................. 18-34
Software Watchdog Reset Timing ............................................................................ 18-36
JTAG Test Logic Block Diagram ............................................................................... 19-2
JTAG TAP Controller State Machine......................................................................... 19-4
Disabling JTAG in JTAG Mode ............................................................................... 19-11
Disabling JTAG in Debug Mode .............................................................................. 19-11
Clock Timing .............................................................................................................. 20-3
PSTCLK Timing......................................................................................................... 20-3
AC Timings—Normal Read and Write Bus Cycles ................................................... 20-5
SDRAM Read Cycle with EDGESEL Tied to Buffered BCLKO.............................. 20-6
SDRAM Write Cycle with EDGESEL Tied to Buffered BCLKO............................. 20-7
SDRAM Read Cycle with EDGESEL Tied High....................................................... 20-8
SDRAM Write Cycle with EDGESEL Tied High...................................................... 20-9
SDRAM Read Cycle with EDGESEL Tied Low ..................................................... 20-10
SDRAM Write Cycle with EDGESEL Tied Low .................................................... 20-11
AC Output Timing—High Impedance...................................................................... 20-11
Reset Timing............................................................................................................. 20-12
Real-Time Trace AC Timing .................................................................................... 20-13
BDM Serial Port AC Timing .................................................................................... 20-13
Timer Module AC Timing ........................................................................................ 20-14
I
UART0/1 Module AC Timing—UART Mode......................................................... 20-17
General-Purpose I/O Timing..................................................................................... 20-18
DMA Timing ............................................................................................................ 20-19
IEEE 1149.1 (JTAG) AC Timing ............................................................................. 20-21
2
C Input/Output Timings......................................................................................... 20-16
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