MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 251

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

SDRAMs operate differently than asynchronous DRAMs, particularly in the use of data
pipelines and commands to initiate special actions. Commands are issued to memory using
specific encodings on address and control pins. Soon after system reset, a command must
be sent to the SDRAM mode register to configure SDRAM operating parameters. Note that,
after synchronous operation is selected by setting DCR[SO], DRAM controller registers
reflect the synchronous operation and there is no way to return to asynchronous operation
without resetting the processor.
11.4.1 DRAM Controller Signals in Synchronous Mode
Table 11-11 shows the behavior of DRAM signals in synchronous mode.
Command
SRAS
SCAS
DRAMW
RAS[1:0]
SCKE
CAS[3:0]
Signal
SELFX
WRITE
READ
ACTV
PALL
SELF
MRS
NOP
REF
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched
by the SDRAM. SRAS should be connected to the corresponding SDRAM SRAS. Do not confuse SRAS
with the DRAM controller’s RAS[1:0], which should not be interfaced to the SDRAM SRAS signals.
Synchronous column address strobe. Indicates a valid column address is present and can be latched by
the SDRAM. SCAS should be connected to the corresponding signal labeled SCAS on the SDRAM. Do
not confuse SCAS with the DRAM controller’s CAS[3:0] signals.
DRAM read/write. Asserted for write operations and negated for read operations.
Row address strobe. Select each memory block of SDRAMs connected to the MCF5307. One RAS
signal selects one SDRAM block and connects to the corresponding CS signals.
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs.
Enables and disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down
mode where operations are suspended or they can enter self-refresh mode. SCKE functionality is
controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SCKE to provide
command-bit functionality.
Column address strobe. For synchronous operation, CAS[3:0] function as byte enables to the SDRAMs.
They connect to the DQM signals (or mask qualifiers) of the SDRAMs.
Activate. Executed before
Mode register set.
No-op. Does not affect SDRAM state machine; DRAM controller control signals negated; RAS asserted.
Precharge all. Precharges all internal banks of an SDRAM component; executed before new page is
opened.
Read access. SDRAM registers column address and decodes that a read access is occurring.
Refresh. Refreshes internal bank rows of an SDRAM component.
Self refresh. Refreshes internal bank rows of an SDRAM component when it is in low-power mode.
Exit self refresh. This command is sent to the DRAM controller when DCR[IS] is cleared.
Write access. SDRAM registers column address and decodes that a write access is occurring.
Table 11-11. Synchronous DRAM Signal Connections
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 11-10. SDRAM Commands
READ
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or
WRITE
executes; SDRAM registers and decodes row address.
Description
Definition
Synchronous Operation
11-17