MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 284

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

DMA Controller Module Programming Model
12.4.1 Source Address Registers (SAR0–SAR3)
SARn, Figure 12-4, contains the address from which the DMA controller requests data. In
single-address mode, SARn provides the address regardless of the direction.
1
Address
12-6
Channel
Reset
On the original MCF5307 mask set (H55J), the BCR of the DMA channels can accommodate only 16 bits.
However, because the revised MCF5307 supports a 24-bit byte count range, the position of the BCR in the
memory map depends on whether a 16- or 24-bit byte counter is selected. The 24-bit byte count can be
selected by setting BCR24BIT = 1, making DCR[AT] available. The AT bit selects whether DMA channels
assert acknowledge during the entire transfer or only at the final transfer of a DMA transaction.
New applications should take advantage of the full range of the 24-bit byte counter, including the AT bit. The
16-bit byte count option (BCR24BIT = 0) retains compatibility with older MCF5307 revisions.
DMA
Field
R/W
3
Table 12-2. Memory Map for DMA Controller Module Registers (Continued)
31
0x3CC
0x3CC
MBAR
Offset
0x3C0
0x3C4
0x3C8
0x3D0
0x3D4
External masters cannot access MCF5307 on-chip memories or
MBAR, but they can access DMA module registers.
SAR/DAR address ranges cannot be programmed to on-chip
SRAM because it cannot be accessed by on-chip DMA.
DMA status register 3
DMA interrupt vector
register 3 (DIVR3)
(DSR3) [p. 12-10]
Byte count register 3 (BCR24BIT = 0)
Figure 12-4. Source Address Registers (SARn)
Reserved
[p. 12-11]
[31:24]
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MBAR + 0x300, 0x340, 0x380, 0x3C0
MCF5307 User’s Manual
Destination address register 3 (DAR3) [p. 12-7]
Source address register 3 (SAR3) [p. 12-6]
DMA control register 3 (DCR3) [p. 12-8]
Byte count register 3 (BCR24BIT = 1)
[23:16]
NOTE:
NOTE:
SAR
R/W
1
Reserved
Reserved
[15:8]
Reserved
1
(BCR3) [p. 12-7]
[7:0]
0