MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 293

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Although Figure 12-11 does not show TM0 signaling a DMA acknowledgement, this signal
can provide an external request acknowledge response, as shown in subsequent diagrams.
To initiate a request, DREQ need only be asserted long enough to be sampled on one rising
clock edge. However, note the following regarding the negation of DREQ:
Figure 12-12 shows a dual-address, peripheral-to-SDRAM DMA transfer. The DMA is not
parked on the bus, so the diagram shows how the CPU can generate multiple bus cycles
during DMA transfers. It also shows TM0 timing. The TT signals indicate whether the CPU
(0) or DMA (1) has bus mastership. TM2 indicates dual-address mode.
If DCR[AT] is 1, TM is asserted during the final transfer. If DCR[AT] is 0, TM asserts
during all DMA accesses.
• In cycle-steal mode (DCR[CS] = 1), the read/write transaction is limited to a single
• In burst mode, (DCR[CS] = 0), multiple read/write transfers can occur on the bus as
transfer. DREQ must be negated appropriately to avoid generating another request.
— For dual-address transfers, DREQ must be negated before TS is asserted for the
— For single-address transfers, DREQ must be negated before TS is asserted for the
programmed. DREQ need not be negated until DSR[DONE] is set, indicating the
block transfer is complete. Another transfer cannot be initiated until the DMA
registers are reprogrammed.
Figure 12-11. DREQ Timing Constraints, Dual-Address DMA Transfer
DREQ0
A[31:0]
CLKIN
write portion, as shown in Figure 12-11, clock cycle 7.
transfer, as shown in Figure 12-13, clock cycle 4.
TM0
R/W
TT1
TT0
CS
TS
TA
0
Freescale Semiconductor, Inc.
1
For More Information On This Product,
Chapter 12. DMA Controller Module
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Go to: www.freescale.com
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4
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DMA Controller Module Functional Description
Read
6
7
8
9
Write
10
11
12-15