MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 379

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

of memory if desired. ADDR_CONFIG is multiplexed with D4 and its configuration is
sampled at reset as shown in Table 17-14.
17.5.7 D[3:2]—Frequency Control PLL (FREQ[1:0])
The frequency control PLL input bus (FREQ[1:0]) indicates the CLKIN frequency range.
These signals are multiplexed with D[3:2] and are sampled during the assertion of RESET.
These signals indicate the operating frequency range to the PLL, as shown in Table 17-15.
Note that these signals do not affect the PLL frequency but are required to set up the analog
PLL.
17.5.8 D[1:0]—Divide Control PCLK to BCLKO (DIVIDE[1:0])
This 2-bit input bus indicates the BCLKO/PSTCLK ratio. These signals are sampled during
the assertion of RESET and indicate the ratios shown in Table 17-16.
17.6 Chip-Select Module Signals
The MCF5307 device provides eight programmable chip-select signals that can directly
interface with SRAM, EPROM, EEPROM, and peripherals. These signals are asserted and
negated on the falling edge of the clock.
D4/ADDR_CONFIG
Table 17-14. D4/ADDR_CONFIG, Address Pin Assignment
0
1
Table 17-16. BCLKO/PSTCLK Divide Ratios
Freescale Semiconductor, Inc.
FREQ[1:0]/D[3:2]
For More Information On This Product,
DIVIDE[1:0]/D[1:0]
Table 17-15. CLKIN Frequency
PP[15:0], defaulted to inputs upon reset
A[31:24]/TIP/DREQ[1:0]/TM[2:0]/TT[1:0]
Chapter 17. Signal Descriptions
00
01
10
11
00
01
10
11
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PAR Configuration at Reset
CLKIN Frequency (MHz)
Ratio of BCLKO/PSTCLK
16.6–27.999
28–38.999
Reserved
Reserved
39–45
1/4
1/2
1/3
Chip-Select Module Signals
17-15