MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 475

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

A
Accumulator (ACC), 2-28
Addressing
Arbitration
B
Baud rates
Bus operation
mode summary, 2-33
variant, 5-5
between masters, 6-14
bus control, 6-11
for internal transfers, 6-12
calculating, 14-19
arbitration control, 6-11
characteristics, 18-2
control signals, 18-1
data transfer
errors, 18-17
external master transfers
features, 18-1
interrupt exceptions, 18-17
master park register, 6-11
misaligned operands, 18-16
reset
back-to-back cycles, 18-10
burst cycles
cycle execution, 18-4
cycle states, 18-5
fast-termination cycles, 18-9
operation, 18-3
read cycle, 18-7
write cycle, 18-8
general, 18-21
two-device arbitration protocol, 18-25
two-wire mode, 18-25
master, 18-34
overview, 18-33
software watchdog, 18-35
line read bus, 18-12
line transfers, 18-12
line write bus, 18-14
mixed port sizes, 18-15
overview, 18-11
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INDEX
Index
C
CCR, 2-28
Chip-select module
Clock
ColdFire core
CPU STOP instruction, 6-10
D
Debug
DMA controller module
DRAM controller
8-, 16-, and 32-bit port sizing, 10-4
enable signals, 17-15
operation, 10-2
overview, 10-1
registers, 10-5, 10-6, A-2
signals, 10-1
PLL control, 6-10
addressing mode summary, 2-33
condition code register (CCR), 2-28
exception processing overview, 2-47
features and enhancements, 2-21
instruction set summary, 2-34
integer data formats, 2-31
MAC registers, 1-14
programming model, 2-26
status register, 2-29
supervisor programming model, 2-29
user programming mode, 2-27
attribute trigger register, 5-7
BDM command set summary, 5-20
breakpoint operation, 5-40
real-time support, 5-39
taken branch, 5-4
theory, 5-40
byte count registers, 12-7
programming model, 12-4
signal description, 12-2
source address registers, 12-6
timing specifications, 20-19
transfer overview, 12-3
asynchronous operation
general, 10-3
global, 10-4
code example, 10-9
control, 10-8
mask, 10-6
Index-17